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embedded pentium ? processor with mmx? technology 200 mhz, 233 mhz datasheet product features the pentium ? processor with mmx? technology provides the performance needed for embedded applications. the pentium processor with mmx technology is compatible with the entire installed base of applications for ms-dos*, windows*, os/2* and unix*. the pentium processor with mmx technology supports intels mmx technology. the pentium processor with mmx technology superscalar architecture can execute two instructions per clock cycle. enhanced branch prediction, a pipelined floating-point unit and separate caches provide high performance. separate code and data caches reduce cache conflicts while remaining software transparent. the pentium processor with mmx technology has 4.5 million transistors and is built on intels enhanced cmos silicon technology. n support for mmx? technology n compatible with large software base ms-dos*, windows*, os/2*, unix* n 32-bit processor with 64-bit data bus n superscalar architecture enhanced pipelines two pipelined integer units capable of two instructions per clock pipelined mmx technology unit pipelined floating-point unit n separate code and data caches 16-kbyte code, 16-kbyte write back data mesi cache protocol n advanced design features deeper write buffers enhanced branch prediction feature virtual mode extensions n enhanced cmos silicon technology n 4-mbyte pages for increased tlb hit rate n ieee 1149.1 boundary scan n dual processing configuration n internal error detection features n multiprocessor support multiprocessor instructions support for second level cache n on-chip local apic controller multiprocessor interrupt management 8259 compatible n power management features system management mode clock control n fractional bus operation 233 mhz core/66 mhz bus (icomp ? index 2.0 rating=203) ? 200 mhz core/66 mhz bus (icomp ? index 2.0 rating=182) ? n plastic pin grid array package ? contact intel corporation for more information about icomp ? index 2.0 ratings. order number: 273214-001 november 1998
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? processor with mmx? technology may contain design defects or errors known as errata which may cause the product to deviate fro m published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners.
datasheet 3 embedded pentium ? processor with mmx? technology contents 1.0 architecture overview .............................................................................................7 1.1 pentium ? processor family architecture ..............................................................8 1.2 embedded pentium ? processor with mmx? technology.................................. 10 1.2.1 full support for intels mmx? technology ............................................ 11 1.2.2 16-kbyte code and data cache ............................................................11 1.2.3 improved branch prediction ...................................................................11 1.2.4 enhanced pipeline ................................................................................. 11 1.2.5 deeper write buffers ..............................................................................11 2.0 packaging information ...........................................................................................12 2.1 pinout .................................................................................................................. 12 2.1.1 pin cross reference ..............................................................................14 2.1.2 design notes..........................................................................................16 2.1.3 pin quick reference ..............................................................................16 2.1.4 pin reference tables.............................................................................24 2.1.5 pin grouping according to function....................................................... 27 2.2 mechanical specifications ................................................................................... 28 2.3 thermal specifications ........................................................................................29 2.4 measuring thermal values .................................................................................29 2.4.1 thermal equations ................................................................................. 30 3.0 electrical specifications ........................................................................................32 3.1 electrical characteristics .....................................................................................32 3.1.1 power supplies ......................................................................................32 3.1.2 power supply sequencing ..................................................................... 32 3.1.3 connection specifications ...................................................................... 32 3.1.3.1 power and ground .................................................................... 33 3.1.3.2 v cc2 and v cc3 measurement specification..............................33 3.1.3.3 decoupling recommendations ................................................. 33 3.1.3.4 3.3-v inputs and outputs .......................................................... 34 3.1.3.5 nc/inc and unused inputs ....................................................... 34 3.1.3.6 private bus ................................................................................34 3.1.4 buffer models .........................................................................................35 3.2 absolute maximum ratings.................................................................................35 3.3 dc specifications ................................................................................................36 3.4 ac specifications ................................................................................................37 figures 1 pentium ? processor with mmx? technology block diagram.............................. 9 2 pentium ? processor with mmx? technology ppga package pinout - top side view ........................................................................................ 12 3 pentium ? processor with mmx? technology ppga package pinout - bottom side view................................................................................... 13 4 ppga package dimensions................................................................................ 28 5 technique for measuring t c on ppga packages...............................................31
embedded pentium ? processor with mmx? technology 4 datasheet 6 thermal resistance vs. heatsink height, ppga packages ............................... 31 7 clock waveform .................................................................................................. 43 8 valid delay timings ............................................................................................ 43 9 float delay timings ............................................................................................ 43 10 setup and hold timings ...................................................................................... 44 11 reset and configuration timings ........................................................................ 44 12 test timings........................................................................................................ 45 13 test reset timings ............................................................................................. 45 14 50 percent v cc measurement of flight time...................................................... 46 tables 1 pin cross-reference by pin name address and data pins........................... 14 2 pin cross-reference by pin name control pins ............................................15 3 pin cross-reference by pin name power, ground and no connect pins .... 16 4 quick pin reference ........................................................................................... 17 5 bus frequency selections ..................................................................................23 6 output pins ......................................................................................................... 24 7 input pins ............................................................................................................25 8 input/output pins ................................................................................................ 26 9 inter-processor input/output pins ....................................................................... 26 10 pin functional grouping...................................................................................... 27 11 ppga package information ................................................................................ 28 12 ppga package dimensions ............................................................................... 28 13 power dissipation requirements for thermal design ........................................ 29 14 thermal resistance for ppga packages ........................................................... 31 15 absolute maximum ratings ................................................................................ 35 16 v cc and t case specifications ............................................................................ 36 17 3.3 v dc specifications ...................................................................................... 36 18 icc specifications............................................................................................... 36 19 input and output characteristics......................................................................... 37 20 ac specifications ................................................................................................ 38 21 notes for table 20 ............................................................................................... 42
datasheet 5 embedded pentium ? processor with mmx? technology revision history date revision description 11/98 001 this is the first publication of this document.

pentium ? processor with mmx? technology datasheet 7 1.0 architecture overview the embedded pentium ? processor with mmx? technology is binary compatible with the 8086/8088, 80286, intel386?, and intel486? processor families, and with other pentium processors. the embedded pentium processor family includes the following products. ? pentium processor ? pentium processor with voltage reduction technology ? pentium processor with mmx technology ? low-power embedded pentium processor with mmx technology the pentium processor family supports the features of previous intel architecture processors, and provides significant enhancements and additions including the following: in addition to the features listed above, the pentium processor with mmx technology offers the following enhancements over the pentium processor: ? support for intel ? mmx technology ? doubled code and data cache sizes to 16 kbytes each ? improved branch prediction ? enhanced pipeline ? deeper write buffers the following features are supported by the pentium processor, but these features are not supported by the pentium processor with mmx technology: ? functional redundancy check and lock-step operation. ? support for intel 82498/82493 and 82497/82492 cache chipset products ? split-line accesses to the code cache for a more detailed description of the pentium processor family products, please refer to the embedded pentium ? processor family developers manual (order number 273204). ? superscalar architecture ? dynamic branch prediction ? pipelined floating-point unit ? improved instruction execution time ? separate code and data caches ? writeback mesi protocol in the data cache ? 64-bit data bus ? bus cycle pipelining ? address parity ? internal parity checking ? execution tracing ? performance monitoring ? ieee 1149.1 boundary scan ? system management mode ? virtual mode extensions ? dual processing support ? on-chip local apic device
pentium ? processor with mmx? technology 8 datasheet 1.1 pentium ? processor family architecture the application instruction set of the pentium processor family includes the complete intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the pentium processor. all application software written for the intel386 and intel486 family of microprocessors runs on pentium processors without modification. the on-chip memory management unit (mmu) is completely compatible with the intel386 family and intel486 family of processors. pentium processors implement several enhancements to increase performance. the two instruction pipelines and the floating-point unit are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in pentium processors. to support this, the processor has two prefetch buffers: one prefetches code in a linear fashion and the other prefetches code according to the btb so the needed code is almost always prefetched before it is needed for execution. the floating-point unit (fpu) is up to ten times faster than the fpu used on the intel486 processor for common operations including add, multiply, and load. pentium processors include separate code and data caches that are integrated on-chip to meet performance goals. each cache has a 32-byte line size. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be write back or write through on a line-by-line basis and follows the mesi protocol. the data cache tags are triple-ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are multi-ported to support snooping. individual pages can be configured as cacheable or non- cacheable by software or hardware. the caches can be enabled or disabled by software or hardware. pentium processors have a 64-bit data bus for fast data transfer. burst read and burst writeback cycles are supported. in addition, bus cycle pipelining allows two bus cycles to occur simultaneously. the memory management unit contains optional extensions to the architecture which allow 4-kbyte and 4-mbyte page sizes. pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking and internal parity checking features have been added along with a new exception, the machine check exception. as more and more functions are integrated on chip, the complexity of board level testing is increased. to address this, pentium processors have increased test and debug capability. pentium processors implement ieee boundary scan (standard 1149.1). in addition, pentium processors provide four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. figure 1 is a block diagram of the embedded pentium processor with mmx technology.
pentium ? processor with mmx? technology datasheet 9 the block diagram shows the two instruction pipelines, the u pipe and the v pipe. the u-pipe can execute all integer and floating-point instructions. the v-pipe can execute simple integer instructions and the fxch floating-point instructions. the separate code and data caches are shown in the block diagram. the data cache has two ports, one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. figure 1. pentium ? processor with mmx? technology block diagram a6180-01 dp logic control rom control unit address generate (u pipeline) address generate (v pipeline) control bus unit 64-bit data bus 32-bit address bus control apic tlb data cache 16 kbytes data control branch target buffer mmx ? unit prefetch address instruction pointer prefetch buffers instruction decode code cache 16 kbytes tlb 128 64 32 32 32 32 32 32 80 80 control add floating point unit register file 64-bit data bus 32-bit addr. bus 32 integer register file alu (u pipline) alu (v pipline) barrel shifter branch verification and target address divide multiply page unit u-pipeline connection v-pipeline connection
pentium ? processor with mmx? technology 10 datasheet the decode unit decodes the prefetched instructions so the processor can execute the instruction. the control rom contains microcode to control the sequence of operations that must be performed to implement the pentium processor architecture. the control rom unit has direct control over both pipelines. pentium processors contain a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. symmetric dual processing in a system is supported with two pentium processors. the two processors appear to the system as a single pentium processor. operating systems with dual processing support properly schedule computing tasks between the two processors. this scheduling of tasks is transparent to software applications and the end-user. logic built into the processors support a glueless interface for easy system design. through a private bus, the two pentium processors arbitrate for the external bus and maintain cache coherency. dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. in this document, in order to distinguish between two pentium processors in dual processing mode, one processor is the primary processor and the other is the dual processor. the pentium processor supports clock control. when the clock to the processor is stopped, power dissipation is virtually eliminated. the combination of these improvements makes the pentium processor a good choice for energy-efficient designs. the pentium processor supports fractional bus operation. this allows the internal processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. the pentium processor contains an on-chip advanced programmable interrupt controller (apic). this apic implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple i/o subsystem support, 8259a compatibility, and inter-processor interrupt support. the architectural features introduced in this chapter are more fully described in the embedded pentium ? processor family developer's manual (order number 273204). 1.2 embedded pentium ? processor with mmx? technology the embedded pentium processor with mmx technology is software and pin compatible with other members of the embedded pentium processor family. it contains 4.5 million transistors and is manufactured on lntels enhanced 0.35 micron cmos process which allows voltage reduction technology for low power and high density. this enables the embedded pentium processor with mmx technology to remain within the thermal envelope of the embedded pentium processor while providing a significant performance increase. the pentium processor with mmx technology has several additional micro-architectural enhancements compared to the pentium processor. the additions are described in the following sections.
pentium ? processor with mmx? technology datasheet 11 1.2.1 full support for intels mmx? technology mmx technology is based on the single instruction multiple data (simd) technique which enables increased performance on a wide variety of multimedia and communications applications. fifty-seven new instructions and four new 64-bit data types are supported in the embedded pentium processor with mmx technology. all existing operating system and application software are fully- compatible with the embedded pentium processor with mmx technology. 1.2.2 16-kbyte code and data cache on-chip, level-one (l1) data and code cache sizes have been doubled to 16 kbytes each. these caches are 4-way set associative. larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently-used instructions and data. the instruction and data caches can be accessed simultaneously. the data cache supports two data references simultaneously. the data cache supports a write back policy (or alternatively, write- through, on a line-by-line basis) for memory updates. by default, the code cache is write-protected. 1.2.3 improved branch prediction dynamic branch prediction uses the branch target buffer (btb) to boost performance by predicting the most likely set of instructions to be executed. the btb has been improved to increase its accuracy. the embedded pentium processor with mmx technology has four prefetch buffers that can hold up to four successive code streams. 1.2.4 enhanced pipeline an additional pipeline stage has been added and the pipeline has been enhanced to improve performance. the integration of the mmx technology pipeline with the integer pipeline is very similar to that of the floating-point pipeline. under some circumstances, two mmx instructions or one integer and one mmx instruction can be paired and issued in one clock cycle to increase throughput. the enhanced pipeline is described in more detail in the embedded pentium ? processor family developer's manual (order number 273204). 1.2.5 deeper write buffers a pool of four write buffers is now shared between the dual pipelines to improve memory write performance.
pentium ? processor with mmx? technology 12 datasheet 2.0 packaging information 2.1 pinout figure 2. pentium ? processor with mmx? technology ppga package pinout - top side view a6174-01 inc inc inc flush# vcc2 vcc3 a10 a6 nc adsc# eads# w/r# vss vss vss vss vss vss vss vss vss vss vss vss a8 a4 a30 vcc2 det# pwt hitm# buschk# be0# be2# be4# be6# scyc a20 a18 a16 a14 a12 a11 a7 a3 ap d/c# hit# a20m# be1# be3# be5# be7# clk reset a19 a17 a15 a13 a9 a5 a29 a28 a25 a31 a26 a22 vcc3 a24 a27 a21 vss d/p# a23 intr vss r/s# nmi smi# vss init ignne# pen# vss vss stpclk# vss vss nc vss trst# tms vss tdo tdi tck vss picd1 d0 vss picd0 d2 picclk vss d3 d1 d5 d4 d7 d6 dp0 d8 d12 dp1 d9 d10 d14 d17 d21 d11 d13 d16 d20 nc d15 d18 d22 vcc3 breq hlda ads# vss lock# vcc2 smiact# pcd vss pchk# pbreq# apchk# vss pbgnt# phitm# prdy vss hold phit# wb/wt# vss boff# brdyc# na# vss brdy# ewbe# ken# vss ahold cache# inv vss mi/o# bp2 bp3 vss pm1bp1 pm0bp0 ferr# vss ierr# d63 dp7 vss d62 d61 d60 vss d59 d57 d58 vss d56 d55 d53 dp6 d51 dp5 d54 d52 d49 d46 d42 d50 d48 d44 d40 d39 inc d47 d45 dp4 d38 d36 inc d43 vss vss vss vss vss vss vss vss vss vss vss vss d37 d35 d33 dp3 d30 d34 d32 d31 d29 d27 inc d41 vcc2 d28 d25 d26 dp2 d23 d24 d19 vcc3 vcc3 nc nc vcc3 vss nc nc bf1 bf0 vss vss vss nc cputyp an 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 nc top side view
pentium ? processor with mmx? technology datasheet 13 figure 3. pentium ? processor with mmx? technology ppga package pinout - bottom side view a6173-01 inc inc inc flush# vcc2 vcc3 a10 a6 nc adsc# eads# w/r# vss vss vss vss vss vss vss vss vss vss vss vss a8 a4 a30 pwt hitm# buschk# be0# be2# be4# be6# scyc a20 a18 a16 a14 a12 a11 a7 a3 ap d/c# hit# a20m# be1# be3# be5# be7# clk reset a19 a17 a15 a13 a9 a5 a29 a28 a25 a31 a26 a22 vcc3 a24 a27 a21 vss d/p# a23 intr vss r/s# nmi smi# vss init ignne# pen# vss nc vss stpclk# vss vss nc vss trst# cputyp tms vss tdo tdi tck vss picd1 d0 vss picd0 d2 picclk vss d3 d1 d5 d4 d7 d6 dp0 d8 d12 dp1 d9 d10 d14 d17 d21 d11 d13 d16 d20 nc d15 d18 d22 vcc3 breq hlda ads# vss lock# vcc2 smiact# pcd vss pchk# pbreq# apchk# vss pbgnt# phitm# prdy vss hold phit# wb/wt# vss boff# brdyc# na# vss brdy# ewbe# ken# vss ahold cache# inv vss mi/o# bp2 bp3 vss pm1bp1 pm0bp0 ferr# vss ierr# d63 dp7 vss d62 d61 d60 vss d59 d57 d58 vss d56 d55 d53 dp6 d51 dp5 d54 d52 d49 d46 d42 d50 d48 d44 d40 d39 d47 d45 dp4 d38 d36 inc inc d43 vss vss vss vss vss vss vss vss vss vss vss vss d37 d35 d33 dp3 d30 d34 d32 d31 d29 d27 inc d41 vcc2 d28 d25 d26 dp2 d23 d24 d19 vcc3 vcc3 nc nc vcc3 vss nc nc bf1 bf0 vss vss vss nc an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10111213141516 1718 192021222324 2526 2728293031323334353637 an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10111213 1415161718192021 22232425262728 293031323334353637 vcc2 det# vcc2 vcc2 vcc2 vcc2 vcc2 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 pin side view
pentium ? processor with mmx? technology 14 datasheet 2.1.1 pin cross reference table 1. pin cross-reference by pin name address and data pins pin location pin location pin location pin location pin location address a3 al35 a9 ak30 a15 ak26 a21 af34 a27 ag33 a4 am34 a10 an31 a16 al25 a22 ah36 a28 ak36 a5 ak32 a11 al31 a17 ak24 a23 ae33 a29 ak34 a6 an33 a12 al29 a18 al23 a24 ag35 a30 am36 a7 al33 a13 ak28 a19 ak22 a25 aj35 a31 aj33 a8 am32 a14 al27 a20 al21 a26 ah34 data d0 k34 d13 b34 d26 d24 d39 d10 d52 e03 d1 g35d14c33d27c21d40d08d53g05 d2 j35 d15 a35 d28 d22 d41 a05 d54 e01 d3 g33 d16 b32 d29 c19 d42 e09 d55 g03 d4 f36 d17 c31 d30 d20 d43 b04 d56 h04 d5 f34 d18 a33 d31 c17 d44 d06 d57 j03 d6 e35 d19 d28 d32 c15 d45 c05 d58 j05 d7 e33 d20 b30 d33 d16 d46 e07 d59 k04 d8 d34 d21 c29 d34 c13 d47 c03 d60 l05 d9 c37 d22 a31 d35 d14 d48 d04 d61 l03 d10 c35 d23 d26 d36 c11 d49 e05 d62 m04 d11 b36 d24 c27 d37 d12 d50 d02 d63 n03 d12 d32 d25 c23 d38 c09 d51 f04
pentium ? processor with mmx? technology datasheet 15 ta ble 2 . pin cross-reference by pin name control pins pin location pin location pin location pin location control a20m# ak08 breq aj01 hit# ak06 prdy ac05 ads# aj05 buschk# al07 hitm# al05 pwt al03 adsc# am02 cache# u03 hlda aj03 r/s# ac35 ahold v04 cputyp q35 hold ab04 reset ak20 ap ak02 d/c# ak04 ierr# p04 scyc al17 apchk# ae05 d/p# ae35 ignne# aa35 smi# ab34 be0# al09 dp0 d36 init aa33 smiact# ag03 be1# ak10 dp1 d30 intr/lint 0 ad34 tck m34 be2# al11 dp2 c25 inv u05 tdi n35 be3# ak12 dp3 d18 ken# w05 tdo n33 be4# al13 dp4 c07 lock# ah04 tms p34 be5# ak14 dp5 f06 m/io# t04 trst# q33 be6# al15 dp6 f02 na# y05 vcc2det# al01 be7# ak16 dp7 n05 nmi/lint1 ac33 w/r# am06 boff# z04 eads# am04 pcd ag05 wb/wt# aa05 bp2 s03 ewbe# w03 pchk# af04 bp3 s05 ferr# q05 pen# z34 brdy# x04 flush# an07 pm0/bp0 q03 brdyc# y03 frcmc# 1 y35 pm1/bp1 r04 apic picclk h34 2 picd0/[dp en#] j33 picd1/[api cen] l35 clock control clk ak18 2 [bf0] y33 [bf1] x34 stpclk# v34 dual processor private interface pbgnt# ad04 pbreq# ae03 phit# aa03 phitm# ac03 notes: 1. the frcmc# pin is not defined for the pentium ? processor with mmx? technology. this pin should be left as a nc or tied to v cc3 via an external pull-up resistor on the pentium processor with mmx technology. 2. picclk and clk are 3.3 v-tolerant-only on the pentium processor with mmx technology. please refer to the embedded pentium ? processor family developer's manual (order number 273204) for the clk and picclk signal quality specification.
pentium ? processor with mmx? technology 16 datasheet 2.1.2 design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to gnd. note: no connect (nc) pins must remain unconnected. connection of nc or inc pins may result in component failure or incompatibility with future processor steppings. 2.1.3 pin quick reference this section gives a brief functional description of each of the pins. for a detailed description, see the hardware interface chapter in the embedded pentium ? processor family developer's manual (order number 273204). note: all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. square brackets around a signal name indicate that the signal is defined only at reset. the following pins become i/o pins when two pentium processors with mmx technology are operating in a dual processing environment: ads#, cache#, hit#, hitm#, hlda#, lock#, m/io#, d/c#, w/r#, scyc, be4# table 3. pin cross-reference by pin name power, ground and no connect pins v cc2 a17 a11 g01 n01 u01 aa01 ae01 an09 an13 an17 a15 a09 j01 q01 w01 ac01 ag01 an11 an15 an19 a13 a07 l01 s01 y01 v cc3 a19 a25 e37 l37 q37 u33 y37 ae37 an27 an21 a21 a27 g37 l33 s37 u37 aa37 ag37 an25 a23 a29 j37 n37 t34 w37 ac37 an29 an23 v ss b06 b18 h02 p02 t36 x36 ad02 aj37 am14 am24 b08 b20 h36 p36 u35 z02 ad36 al37 am16 am26 b10 b22 k02 r02 v02 z36 af02 am08 am18 am28 b12 b24 k36 r36 v36 ab02 af36 am10 am20 am30 b14 b26 m02 t02 x02 ab36 ah02 am12 am22 an37 b16 b28 m36 nc a37 r34 s33 s35 w33 w35 al19 an35 y35 inc a03 b02 c01 an01 an03 an05
pentium ? processor with mmx? technology datasheet 17 table 4. quick pin reference (sheet 1 of 7) symbol type name and function a20m# i when the address bit 20 mask pin is asserted, the processor emulates the address wraparound at 1 mbyte which occurs on the 8086 by masking physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a20m# is internally masked by the processor when configured as a dual processor. a31Ca3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31Ca5. ads# o the address strobe indicates that a new valid bus cycle is currently being driven by the processor. adsc# o the address strobe (copy) is functionally identical to ads#. ahold i in response to the assertion of address hold , the pentium ? processor with mmx? technology stops driving the address lines (a31Ca3) and ap in the next clock. the rest of the bus remains active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the processor with even parity information on all processor generated cycles in the same clock that the address is driven. even parity must be driven back to the processor during inquire cycles on this pin in the same clock as eads# to ensure that correct parity check status is indicated by the processor. apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active when the processor has detected a parity error on the address bus during inquire cycles. apchk# remains active for one clock each time a parity error is detected (including during dual processing private snooping). [apicen] picd1 i advanced programmable interrupt controller enable enables or disables the on-chip apic interrupt controller. when sampled high at the falling edge of reset, the apic is enabled. apicen shares a pin with the picd1 signal. be7#Cbe4# be3#Cbe0# o i/o the byte enable pins are used to determine which bytes must be written to external memory or which bytes were requested by the processor for the current cycle. the byte enables are driven in the same clock as the address lines (a31C a3). additionally, the lower 4-byte enables (be3#Cbe0#) are used on the pentium processor with mmx technology as apic id inputs and are sampled at reset. in dual processing mode, be4# is used as an input during flush cycles. bf1Cbf0 i the bus frequency pins determine the bus-to-core frequency ratio. bf1Cbf0 are sampled at reset, and cannot be changed until another non-warm (1 ms) assertion of reset. additionally, bf1Cbf0 must not change values while reset is active. see table 5 for bus frequency selections. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the processor floats all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the processor restarts the aborted bus cycle(s) in their entirety. bp3Cbp2 pm1Cpm0/ bp1Cbp0 o the breakpoint pins (bp3Cbp0) correspond to the debug registers, dr3Cdr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring.
pentium ? processor with mmx? technology 18 datasheet brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. brdyc# i the burst ready (copy) is functionally identical to brdy#. breq o the bus request output indicates to the external system that the processor has internally generated a bus request. this signal is always driven whether or not the processor is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, the processor latches the address and control signals in the machine check registers. when the mce bit in cr4 is set and the buschk# pin is active, the processor vectors to the machine check exception. to assure that buschk# is always recognized, stpclk# must be deasserted any time buschk# is asserted by the system, before the system allows another external bus cycle. when buschk# is asserted by the system for a snoop cycle while stpclk# remains asserted, usually (if mce=1) the processor vectors to the exception after stpclk# is deasserted. but if another snoop to the same line occurs during stpclk# assertion, the processor can lose the buschk# request. cache# o for processor-initiated cycles, the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst write back cycle (when a write). when this pin is driven inactive during a read cycle, the processor does not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for the processor. its frequency is the operating frequency of the processor external bus, and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst#, and picd0Cpicd1 are specified with respect to the rising edge of clk. this pin is 3.3-v-tolerant-only on the pentium processor with mmx technology. please refer to the embedded pentium ? processor family developers manual (order number 273204) for the clk and picclk signal quality specification. it is recommended that clk begin toggling within 150 ms after v cc reaches its proper operating level. this recommendation is to ensure long-term reliability of the device. cputyp i cpu type distinguishes the primary processor from the dual processor. in a single processor environment, or when the processor is acting as the primary processor in a dual processing system, cputyp should be strapped to v ss . the dual processor should have cputyp strapped to v cc3 . d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. d/p# o the dual/primary processor indication. the primary processor drives this pin low when it is driving the bus, otherwise it drives this pin high. d/p# is always driven. d/p# can be sampled for the current cycle with ads# (like a status pin). this pin is defined only on the primary processor. dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. within these restrictions, two processors of different steppings may operate together in a system. d63Cd0 i/o these are the 64 data lines for the processor. lines d7Cd0 define the least significant byte of the data bus; lines d63Cd56 define the most significant byte of the data bus. when the processor is driving the data lines, they are driven during the t2, t12, or t2p clocks for that cycle. during reads, the processor samples the data bus when brdy# is returned. table 4. quick pin reference (sheet 2 of 7) symbol type name and function
pentium ? processor with mmx? technology datasheet 19 dp7Cdp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the processor with even parity information on writes in the same clock as write data. even parity information must be driven back to the processor on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the processor. dp7 applies to d63Cd56, dp0 applies to d7Cd0. [dpen#] picd0 i/o dual processing enable is an output of the dual processor and an input of the primary processor. the dual processor drives dpen# low to the primary processor at reset to indicate that the primary processor should enable dual processor mode. dpen# may be sampled by the system at the falling edge of reset to determine if the dual-processor socket is occupied. dpen# is multiplexed with picd0. eads# i this signal indicates that a valid external address has been driven onto the processor address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the processor generates a write, and ewbe# is sampled inactive, the processor holds off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, which is indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using dos-type floating-point error reporting. ferr# is never driven active by the dual processor. flush# i when asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle will be generated by the processor to indicate the completion of the write back and invalidation. when flush# is sampled low when reset transitions from high to low, three- state test mode is entered. when two pentium processors with mmx technology are operating in dual processing mode and flush# is asserted, the dual processor performs a flush first (without a flush acknowledge cycle), then the primary processor performs a flush followed by a flush acknowledge cycle. when the flush# signal is asserted in dual processing mode, it must be deasserted at least one clock prior to brdy# of the flush acknowledge cycle to avoid dp arbitration problems. hit# o the hit indication is driven to reflect the outcome of an inquire cycle. when an inquire cycle hits a valid line in the processor data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. when the inquire cycle misses the processor cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda will be driven inactive and the pentium processor with mmx technology will resume driving the bus. if the processor has a bus cycle pending, it will be driven one clock cycle after hlda is deasserted. table 4. quick pin reference (sheet 3 of 7) symbol type name and function
pentium ? processor with mmx? technology 20 datasheet hold i in response to the bus hold request , the processor floats most of its output and input/output pins and asserts hlda after completing all outstanding bus cycles. the processor maintains its bus in this state until hold is deasserted. hold is not recognized during lock cycles. the processor recognizes hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. when a parity error occurs on a read from an internal array, the processor asserts the ierr# pin for one clock and then shuts down. ignne# i this is the ignore numeric error input. this pin has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0, and the ignne# pin is asserted, the processor ignores any pending unmasked numeric exception and continues executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor executes the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor stops execution and waits for an external interrupt. ignne# is internally masked when the processor is configured as a dual processor. init i the processor initialization input pin forces the processor to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating-point registers retain the values they had prior to init. init may not be used instead of reset after power-up. when init is sampled high when reset transitions from high to low, the processor performs a built-in self test prior to the start of program execution. intr/lint0 i an active maskable interrupt input indicates that an external interrupt has been generated. when the if bit in the eflags register is set, the processor generates two locked interrupt acknowledge bus cycles and vectors to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to ensure that the interrupt is recognized. when the local apic is enabled, this pin becomes lint0. inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the processor generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle is transformed into a burst line fill cycle. lint0/intr i when the apic is enabled, this pin is local interrupt 0 . when the apic is disabled, this pin is intr. lint1/nmi i when the apic is enabled, this pin is local interrupt 1 . when the apic is disabled, this pin is nmi. lock# o the bus lock pin indicates that the current bus cycle is locked. the pentium processor with mmx technology does not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be deasserted for at least one clock between back-to-back locked cycles. table 4. quick pin reference (sheet 4 of 7) symbol type name and function
pentium ? processor with mmx? technology datasheet 21 m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the processor issues ads# for a pending cycle two clocks after na# is asserted. the processor supports up to two outstanding bus cycles. nmi/lint1 i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. when the local apic is enabled, this pin becomes lint1. pbgnt# i/o private bus grant is the grant line that is used when two pentium processors with mmx technology are configured in dual processing mode, in order to perform private bus arbitration. pbgnt# should be left unconnected if only one pentium processor with mmx technology exists in a system. pbreq# i/o private bus request is the request line that is used when two pentium processors with mmx technology are configured in dual processing mode, in order to perform private bus arbitration. pbreq# should be left unconnected when only one processor exists in a system. pcd o the page cache disable pin reflects the state of the pcd bit in cr3, the page directory entry, or the page table entry. pcd provides an external cacheability indication on a page by page basis. pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. when two pentium processors with mmx technology are operating in dual processing mode, pchk# may be driven two or three clocks after brdy# is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. when this pin is sampled active in the clock a data parity error is detected, the processor latches the address and control signals of the cycle with the parity error in the machine check registers. when pen# is sampled active and the machine check enable bit in cr4 is set to 1, the processor vectors to the machine check exception before the beginning of the next instruction. phit# i/o private hit is a hit indication used when two pentium processors with mmx technology are configured in dual processing mode, in order to maintain local cache coherency. phit# should be left unconnected when only one processor exists in a system. phitm# i/o private modified hit is a hit on a modified cache line indication used when two pentium processors with mmx technology are configured in dual processing mode, in order to maintain local cache coherency. phitm# should be left unconnected if only one processor exists in a system. picclk i the apic interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the processor. this pin is 3.3-v-tolerant-only on the pentium processor with mmx technology. please refer to the embedded pentium ? processor family developers manual (order number 273204) for the clk and picclk signal quality specification. picd0/[dpen#]C picd1/[apicen] i/o programmable interrupt controller data lines 0 C 1 of the pentium processor with mmx technology comprise the data portion of the apic 3-wire bus. they are open-drain outputs that require external pull-up resistors. these signals are multiplexed with dpen# and apicen respectively. table 4. quick pin reference (sheet 5 of 7) symbol type name and function
pentium ? processor with mmx? technology 22 datasheet pm1/bp1C pm0/bp0 o these pins function as part of the performance monitoring feature. the breakpoint 1C0 pins are multiplexed with the performance monitoring 1 C 0 pins. the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin is provided for use with the intel debug port. please refer to the embedded pentium ? processor family developers manual (order number 273204) for more details. pwt o the page write through pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external write back indication on a page-by-page basis. r/s# i the run/stop input is provided for use with the intel debug port. please refer to the embedded pentium ? processor family developers manual (order number 273204) for more details. reset i reset forces the processor to begin execution at a known state. all the processor internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush# and init are sampled when reset transitions from high to low to determine if three-state test mode or checker mode will be entered, or if built-in self-test (bist) will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles which are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the processor, thereby causing the core to consume less power. when the processor recognizes stpclk#, the processor stops execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generates a stop grant acknowledge cycle. when stpclk# is asserted, the processor still responds to interprocessor and external snoop requests. tck i the testability clock input provides the clocking function for the processor boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the processor during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the processor on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the processor on the tdo pin on tcks falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. vcc2 i the pentium processor with mmx technology has 25 2.8 v power inputs. vcc3 i the pentium processor with mmx technology has 28 3.3 v power inputs. vcc2det# o v cc2 detect is used in flexible motherboard implementations to configure the voltage output set-point appropriately for the v cc2 inputs of the processor. table 4. quick pin reference (sheet 6 of 7) symbol type name and function
pentium ? processor with mmx? technology datasheet 23 core and bus frequencies can be set according to table 5. each pentium processor with mmx technology is specified to operate within a single bus-to-core ratio and a specific minimum-to- maximum bus-frequency range (corresponding to a minimum-to-maximum core-frequency range). operation in other bus-to-core ratios or outside the specified operating frequency range is not supported or advocated. for example, the 166 mhz pentium processor with mmx technology does not operate beyond the 66 mhz bus frequency and only supports the 2/5 bus-to-core ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. vss i the pentium processor with mmx technology has 53 ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the write back/write through input allows a data cache line to be defined as write back or write through on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. table 4. quick pin reference (sheet 7 of 7) symbol type name and function table 5. bus frequency selections bf1 bf0 bus/core ratio max bus/core frequency (mhz) min bus/core frequency (mhz) 0 1 1/3 66/200 33/100 00 2/5 n/a (2) n/a (2) 10 1/2 (1,2) n/a (2) n/a (2) 1 1 2/7 66/233 33/117 notes: 1. this is the default bus to core ratio for the pentium ? processor with mmx? technology. if the bf pins are left floating, the processor will be configured for the 1/2 bus to core frequency ratio. 2. currently, there are no embedded products that support these bus fractions.
pentium ? processor with mmx? technology 24 datasheet 2.1.4 pin reference tables table 6. output pins name active level when floated ads# (1) low bus hold, boff# adsc# low bus hold, boff# apchk# low be7#Cbe4# low bus hold, boff# breq high cache# (1) low bus hold, boff# d/p# (2) n/a ferr# (2) low hit# (1) low hitm# (1, 3) low hlda (1) high ierr# low lock# (1) low bus hold, boff# m/io# (1) , d/c# (1) , w/r# (1) n/a bus hold, boff# pchk# low bp3Cbp2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc (1) high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir vcc2det# low notes: all output and input/output pins are floated during three-state test mode (except ierr#). 1. these are i/o signals when two pentium ? processors with mmx? technology are operating in dual processing mode. 2. these signals are undefined when the processor is configured as a dual processor. 3. m# pin has an internal pull-up resistor.
pentium ? processor with mmx? technology datasheet 25 table 7. input pins name active level synchronous/ asynchronous internal resistor qualified a20m# ? low asynchronous ahold high synchronous apicen high synchronous/reset pull-up bf0 n/a synchronous/reset pull-down bf1 n/a synchronous/reset pull-up boff# low synchronous brdy# low synchronous pull-up bus state t2, t12, t2p brdyc# low synchronous pull-up bus state t2, t12, t2p buschk# low synchronous pull-up brdy# clk n/a cputyp high synchronous/reset pull-down eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous hold high synchronous ignne# ? low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# lint1Clint0 high asynchronous apicen at reset ken# low synchronous first brdy#/na# na# low synchronous bus state t2, td, t2p nmi high asynchronous pen# low synchronous brdy# picclk high asynchronous pull-up r/s# n/a asynchronous pull-up reset high asynchronous smi# low asynchronous pull-up stpclk# low asynchronous pull-up tck n/a pull-up tdi n/a synchronous/tck pull-up tck tms n/a synchronous/tck pull-up tck trst# low asynchronous pull-up wb/wt# n/a synchronous first brdy#/na# ? undefined when the processor is configured as a dual processor.
pentium ? processor with mmx? technology 26 datasheet table 8. input/output pins name (1) active level when floated qualified (when an input) internal resistor a31Ca3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be3#Cbe0# low address hold, bus hold, boff# reset pull-down (2) d63Cd0 n/a bus hold, boff# brdy# dp7Cdp0 n/a bus hold, boff# brdy# dpen# low reset pull-up picd0 n/a pull-up picd1 n/a pull-down notes: 1. all output and input/output pins are floated during three-state test mode (except tdo, ierr# and tdo). 2. be3#Cbe0# have pull-downs during reset only. table 9. inter-processor input/output pins name active level internal resistor phit# low pull-up phitm# low pull-up pbgnt# low pull-up pbreq# low pull-up note: for proper inter-processor operation, the system cannot load these signals.
pentium ? processor with mmx? technology datasheet 27 2.1.5 pin grouping according to function table 10 organizes the pins with respect to their function. table 10. pin functional grouping function pins clock clk initialization reset, init, bf1Cbf0 address bus a31Ca3, be7#Cbe0# address mask a20m# data bus d63Cd0 address parity ap, apchk# apic support picclk, picd1Cpicd0 data parity dp7Cdp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, adsc#, brdy#, brdyc#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda dual processing private bus control pbgnt#, pbreq#, phit#, phitm# interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3Cbp2 power management stpclk# miscellaneous dual processing cputyp, d/p# debugging r/s#, prdy voltage detection vcc2det#
pentium ? processor with mmx? technology 28 datasheet 2.2 mechanical specifications package summary information is provided in table 11. the mechanical specifications for the pentium processor with mmx technology are provided in table 12 and figure 4. table 11. ppga package information package type total pins pin array package size plastic staggered pin grid array (ppga) 296 37 x 37 1.95 x 1.95 4.95 cm x 4.95 cm figure 4. ppga package dimensions table 12. ppga package dimensions symbol millimeters inches min max notes min max notes a 2.72 3.33 0.107 0.131 a 1 1.83 2.23 0.072 0.088 a 2 1.00 0.039 b 0.40 0.51 0.016 0.020 d 49.43 49.63 1.946 1.954 d 1 45.59 45.85 1.795 1.805 d 2 23.44 23.95 0.923 0.943 e 1 2.29 2.79 0.090 0.110 f 1 17.56 0.692 f 2 23.04 0.907 l 3.05 3.30 0.120 0.130 n 296 lead count 296 lead count s 1 1.52 2.54 0.060 0.100
pentium ? processor with mmx? technology datasheet 29 2.3 thermal specifications the pentium processor with mmx technology is specified for proper operation when case temperature, t case , (t c ) is within the range of 0 c to 70 c. the power dissipation specification in table 13 is provided for designing thermal solutions for operation at a sustained maximum level. this is the worst-case power the device would dissipate in a system for a sustained period of time. this number is provided to assist in the design of a thermal solution for the device. 2.4 measuring thermal values to verify that the proper t c is maintained, it should be measured at the center of the package top surface (opposite of the pins). the measurement is made in the same way with or without a heatsink attached. when a heatsink is attached, a hole (smaller than 0.150 diameter) should be drilled through the heatsink to allow probing the center of the package. see figure 5 for an illustration of how to measure t c . to minimize the measurement errors, use the following approach: ? use 36-gauge or finer diameter k, t, or j type thermocouples. the laboratory testing was done using a thermocouple made by omega (part number 5tc-ttk-36-36). ? attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements. the laboratory testing was done by using omega bond* (part number ob-100). ? attach the thermocouple at a 90-degree angle as shown in figure 5. table 13. power dissipation requirements for thermal design measured at v cc2 =2.8 v and v cc3 =3.3 v parameter typical (1) max (2) unit notes active power 7.9 (3) 7.3 (3) 17.0 (4) 15.7 (4) watts watts 233 mhz 200 mhz stop grant/auto halt powerdown power 2.61 2.41 watts watts 233 mhz, note 5 200 mhz, note 5 stop clock power 0.03 < 0.3 watts all frequencies, note 6 notes: 1. this is the typical power dissipation in a system. this value is expected to be the average value that will be measured in a system using a typical device at v cc2 = 2.8 v running typical applications. this value is highly dependent upon the specific system configuration. typical power specifications are not tested. 2. systems must be designed to thermally dissipate the maximum active power dissipation. it is determined using worst case instruction mix with v cc2 = 2.8 v and v cc3 = 3.3 v and also takes into account the thermal time constants of the package. 3. active power (typ) is the average power measured in a system using a typical device running typical applications under normal operating conditions at nominal v cc and room temperature. 4. active power (max) is the maximum power dissipation under normal operating conditions at nominal v cc2 , worst-case temperature, while executing the worst case power instruction mix. active power (max) is equivalent to thermal design power (max). 5. stop grant/auto halt power down power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. 6. stop clock power dissipation is determined by asserting the stpclk# pin and then removing the external clk input.
pentium ? processor with mmx? technology 30 datasheet ? the hole size should be smaller than 0.150 in diameter. ? make sure there is no contact between thermocouple cement and heatsink base. the contact will affect the thermocouple reading. 2.4.1 thermal equations for the pentium processor with mmx technology, an ambient temperature, t a (air temperature around the processor), is not specified directly. the only restriction is that t c is met. to calculate t a values, use the following equations: t a = t c C ( p * q ca ) q ca = q ja - q jc where: t a and t c =ambient and case temperature (c) q ca = case-to-ambient thermal resistance (oc/watt) q ja = junction-to-ambient thermal resistance (oc/watt) q jc = junction-to-case thermal resistance (oc/watt) p = maximum power consumption (watt) table 14 lists the q jc and q ca values for the pentium processor with mmx technology and a passive heatsink. q jc is thermal resistance from die to package case. q jc values shown in these tables are typical values. the actual q jc values depend on actual thermal conductivity and process of die attach. q ca is thermal resistance from package case to the ambient. q ca values shown in these tables are typical values. the actual q ca values depend on the heatsink design, the interface between the heatsink and the package, the air flow in the system, and thermal interactions between the processor and the surrounding components through the printed-circuit board and the ambient air. figure 6 is a graph of the data from table 14. thermal data collection parameters: ? heatsinks are omni-directional pin aluminum alloy ? features were based on standard extrusion practices for a given height ? pin size ranged from 50 to 129 mils ? pin spacing ranged from 93 to 175 mils ? base thickness ranged from 79 to 200 mils ? heatsink attach was 0.005 of thermal grease ? attach thickness of 0.002" will improve performance approximately 0.3o c/watt
pentium ? processor with mmx? technology datasheet 31 figure 5. technique for measuring t c on ppga packages table 14. thermal resistance for ppga packages heat sink height q jc q ca (c/watt) vs. laminar airflow (linear ft/min) (inches) (c/watt) 0 100 200 400 600 800 0.25 0.4 8.9 7.8 6.4 4.3 3.4 2.8 0.35 0.4 8.6 7.3 5.8 3.8 3.1 2.6 0.45 0.4 8.2 6.8 5.1 3.4 2.7 2.3 0.55 0.4 7.9 6.3 4.5 3.0 2.4 2.1 0.65 0.4 7.5 5.8 4.1 2.8 2.2 1.9 0.80 0.4 6.8 5.1 3.7 2.6 2.0 1.8 1.00 0.4 6.1 4.5 3.4 2.4 1.9 1.6 1.20 0.4 5.7 4.1 3.1 2.2 1.8 1.6 1.40 0.4 5.2 3.7 2.8 2.0 1.7 1.5 none 1.2 12.9 12.2 11.2 7.7 6.3 5.4 figure 6. thermal resistance vs. heatsink height, ppga packages 0 1 2 3 4 5 6 7 8 9 10 0.25 0.35 0.45 0.55 0.65 0.8 1 1.2 1.4 0 100 200 400 600 800 heatsink height (inches) q ca ( c/w) air flow rate (lfm)
pentium ? processor with mmx? technology 32 datasheet 3.0 electrical specifications this section describes the electrical differences between the pentium processor with mmx technology and the pentium processor, and the ac and dc specifications of the pentium processor with mmx technology. 3.1 electrical characteristics when creating a pentium processor with mmx technology design based on an existing pentium processor design, there are a number of electrical differences that require attention. the following sections highlight key electrical issues pertaining to the pentium processor with mmx technology power supplies, connection specifications and buffer models. note that it is possible to design a single motherboard that supports more than one member of the pentium processor family. refer to pentium ? processor flexible motherboard design guidelines (order number 243187) for more information and specific implementation examples. 3.1.1 power supplies the main electrical difference between the pentium processor with mmx technology and the pentium processor is the operating voltage. the pentium processor with mmx technology requires two separate voltage inputs, v cc2 and v cc3 . the v cc2 pins supply power to the pentium processor with mmx technology core, while the v cc3 pins supply power to the processor i/o pins. the pentium processor, on the other hand, requires a single voltage supply for all v cc pins. this single supply powers both the core and i/o pins of the pentium processor. by connecting all the v cc2 pins together and all the v cc3 pins together on separate power islands, pentium processor designs can easily be converted to support the pentium processor with mmx technology. in order to maintain compatibility with pentium processor-based platforms, the pentium processor with mmx technology supports the standard 3.3-v specification on its v cc3 pins. 3.1.2 power supply sequencing there is no specific power sequence required for powering up or powering down the separate v cc2 and v cc3 supplies of the pentium processor with mmx technology. it is recommended that the v cc2 and v cc3 supplies be turned on or off within one second of each other. 3.1.3 connection specifications connection specifications for the power and ground inputs, 3.3-v inputs and outputs, and the nc/inc and unused inputs are discussed in the following sections.
pentium ? processor with mmx? technology datasheet 33 3.1.3.1 power and ground for clean on-chip power distribution, the embedded pentium processor with mmx technology has 28 v cc3 (i/o power), 25 v cc2 (core power) and 53 v ss (ground) inputs. power and ground connections must be made to all external v cc and v ss pins of the pentium processor with mmx technology. on the circuit board, all v cc3 pins must be connected to a 3.3-v v cc plane. all v cc3 pins must be connected to a 2.8-v v cc plane. all v ss pins must be connected to a v ss plane. 3.1.3.2 v cc2 and v cc3 measurement specification the values of v cc2 and v cc3 should be measured at the bottom side of the processor pins using an oscilloscope with a 3 db bandwidth of at least 20 mhz (100 ms/s digital sampling rate). there should be a short isolation ground lead attached to a processor pin on the bottom side of the board. the measurement should be taken at the following v cc /v ss pairs: an13/am10, an21/am18, an29/ am26, ac37/z36, u37/r36, l37/h36, a25/b28, a17/b20, a7/b10, g1/k2, s1/v2, ac1/z2. one-half of these pins are v cc2 while the others are v cc3 ; the operating ranges for the v cc2 and v cc3 pins are specified at different voltages. see table 16 for the specification. the display should show continuous sampling of the voltage line, at 20 mv/div, and 500 ns/div with the trigger point set to the center point of the range. slowly move the trigger to the high and low ends of the specification, and verify that excursions beyond these limits are not observed. there are no allowances for crossing the high and low limits of the voltage specification. for more information on measurement techniques, see voltage guidelines for pentium ? processors with mmx? technology (order number 243186). 3.1.3.3 decoupling recommendations liberal decoupling capacitance should be placed near the pentium processor with mmx technology. the pentium processor with mmx technology, when driving its large address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads. low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. inductance can be reduced by shortening circuit board traces between the pentium processor with mmx technology and decoupling capacitors as much as possible. these capacitors should be evenly distributed around each component on the power plane. capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. for the pentium processor with mmx technology, the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. a typical example would be entering or exiting the stop grant state. another example would be executing a halt instruction, causing the pentium processor with mmx technology to enter the autohalt power down state, or transitioning from halt to the normal state. all of these examples may cause abrupt changes in the power being consumed by the pentium processor with mmx technology. note that the autohalt power down feature is always enabled even when other power management features are not implemented. bulk storage capacitors with a low effective series resistance (esr) in the 10- w to 100- w range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. in order to reduce the esr, it may be necessary to place several bulk storage capacitors in parallel.
pentium ? processor with mmx? technology 34 datasheet these capacitors should be placed near the pentium processor with mmx technology on both the v cc2 and v cc3 plane to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. detailed decoupling recommendations are provided in flexible motherboard design guidelines (order number 243187). note: reducing available bulk capacitance could degrade long term system reliability. 3.1.3.4 3.3-v inputs and outputs the inputs and outputs of the pentium processor with mmx technology comply with the 3.3-v jedec standard levels. both inputs and outputs are also ttl-compatible, although the inputs cannot tolerate voltage swings above the v in3 (max) specification. system support components which use ttl-compatible inputs will interface to the pentium processor with mmx technology without extra logic. this is because the pentium processor drives according to the 5-v ttl specification (but not beyond 3.3 v). for pentium processor with mmx technology inputs, the voltage must not exceed the 3.3-v v in3 (max) specification. system support components can consist of 3.3-v devices or open-collector devices. in an open-collector configuration, the external resistor should be biased to v cc3 . all pins, including the clk and picclk of the pentium processor with mmx technology, are 3.3 v-tolerant-only. when an 8259a interrupt controller is used, for example, the system must provide level converters between the 8259a and the pentium processor with mmx technology. 3.1.3.5 nc/inc and unused inputs important: all nc and inc pins must remain unconnected. for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to v ss (ground). 3.1.3.6 private bus when two pentium processors with mmx technology are operating in dual processor mode, a private bus exists to arbitrate for the processor bus and maintain local cache coherency. the private bus consists of two pinout changes: ? five pins are added: pbreq#, pbgnt#, phit#, phitm#, d/p#. ? ten output pins become i/o pins: ads#, d/c#, w/r#, m/io#, cache#, lock#, hit#, hitm#, hlda, scyc, be4#. the new pins are given ac specifications of valid delays at 0 pf, setup times and hold times. simulate with these parameters and their respective i/o buffer models to guarantee that proper timings are met. the ac specification gives input setup and hold times for the ten signals that become i/o pins. these setup and hold times must be met only when a dual processor is present in the system.
pentium ? processor with mmx? technology datasheet 35 3.1.4 buffer models the structure of the buffer models for the pentium processor with mmx technology and the pentium processor are identical. some of the values of the components have changed to reflect the minor manufacturing process and package differences between the processors. the system should see insignificant differences between the ac behavior of the pentium processor with mmx technology and the pentium processor. simulation of ac timings using the pentium processor with mmx technology buffer models is recommended to ensure robust system designs. pay specific attention to the signal quality restrictions imposed by 3.3-v buffers. 3.2 absolute maximum ratings table 15 provides stress ratings only. functional operation at the absolute maximum ratings is not implied or guaranteed. functional operating conditions are given in the ac and dc specification tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the pentium processor with mmx technology contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the dc specifications is not recommended or guaranteed and extended exposure beyond the dc specifications may affect device reliability. table 15. absolute maximum ratings symbol parameter min max unit storage temperature C65 150 c case temperature under bias C65 110 c v cc3 v cc3 supply voltage with respect to v ss C0.5 4.6 v v cc2 v cc2 supply voltage with respect to v ss C0.5 3.7 v v in3 3-v only buffer dc input voltage C0.5 v cc3 +0.5 (not to exceed v cc3 max) v
pentium ? processor with mmx? technology 36 datasheet 3.3 dc specifications tables 16 through 19 list the dc specifications for the pentium processor with mmx technology. table 16. v cc and t case specifications symbol parameter min nom. max unit notes t case case temperature 0 70 c v cc2 v cc2 voltage 2.7 2.8 2.9 v range = 2.8 3.57% ? v cc3 v cc3 voltage 3.135 3.3 3.6 v range = 3.3 C5%, +9.09% ? ? see v cc2 and v cc3 measurement specification on page 34. table 17. 3.3 v dc specifications symbol parameter min max unit notes v il3 input low voltage C0.3 0.8 v ttl level v ih3 input high voltage 2.0 v cc3 +0.3 v ttl level (1) v ol3 output low voltage 0.4 v ttl level (2, 3) v oh3 output high voltage 2.4 v ttl level (4) notes: 1. parameter measured at nominal v cc3 which is 3.3 v. 2. parameter measured at C4 ma. 3. in dual processing systems, up to a 10 ma load from the second processor may be observed on the pchk# signal. based on silicon characterization data, v ol3 of pchk# will remain less than 400 mv even with a 10 ma load. pchk# v ol3 will increase to approximately 500 mv with a 14 ma load (worst case for a dp system with a 4 ma system load). 4. parameter measured at 3 ma. table 18. icc specifications measured at v cc2 =2.9 v and v cc3 =3.6 v symbol parameter min max unit notes i cc2 power supply current 6500 5700 ma ma 233 mhz 200 mhz ? i cc3 power supply current 750 650 ma ma 233 mhz 200 mhz ? ? this value should be used for power supply design. it was determined using a worst case instruction mix and maximum v cc . power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes.
pentium ? processor with mmx? technology datasheet 37 3.4 ac specifications the ac specifications consist of output delays, input setup requirements and input hold requirements. all ac specifications (with the exception of those for the tap signals and apic signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 volts for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct pentium processor with mmx technology operation. each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays. each pentium processor with mmx technology specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to maximum core frequency range). operation in other bus-to-core ratios or outside the specified operating frequency range is not supported. for example, the 166 mhz pentium processor with mmx technology does not operate beyond the 66 mhz bus frequency and only supports the 2/5 bus-to-core ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. table 5 summarizes these specifications. table 19. input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf guaranteed by design c o output capacitance 20 pf guaranteed by design c i/o i/o capacitance 25 pf guaranteed by design c clk clk input capacitance 15 pf guaranteed by design c tin test input capacitance 15 pf guaranteed by design c tout test output capacitance 20 pf guaranteed by design c tck test clock capacitance 15 pf guaranteed by design i li input leakage current 15 a 0 < v in < v il , v ih > v in > v cc , note 1 i lo output leakage current 15 a 0 < v in < v il , v ih > v in > v cc , note 1 i ih input leakage current 200 a v in = 2.4 v, note 2 i il input leakage current C400 a v in = 0.4 v, notes 3, 4 notes: 1. this parameter is for inputs/outputs without an internal pull-up or pull-down. 2. this parameter is for inputs with an internal pull-down. 3. this parameter is for inputs with an internal pull-up. 4. this specification applies to the hitm# pin when it is driven as an input (e.g., in jtag mode).
pentium ? processor with mmx? technology 38 datasheet table 20. ac specifications (sheet 1 of 4) see table 16 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes frequency 33.33 66.6 mhz 7 t 1a clk period 15.0 30.0 ns 7 t 1b clk period stability 250 ps adjacent clocks, notes 1, 25 t 2 clk high time 4.0 ns 7 2 v, note 1 t 3 clk low time 4.0 ns 7 0.8 v, note 1 t 4 clk fall time 0.15 1.5 ns 7 2.0 v C 0.8 v notes 1, 5 t 5 clk rise time 0.15 1.5 ns 7 0.8 v C 2.0 v notes 1, 5 t 6 a pwt, pcd, cache# valid delay 1.0 7.0 ns 8 t 6b ap valid delay 1.0 8.5 ns 8 t 6c be7#Cbe0#, lock# valid delay 0.9 7.0 ns 8 4 t 6d ads# valid delay 0.8 6.0 ns 8 t 6e adsc#, d/c#, w/r#, scyc, valid delay 0.8 7.0 ns 8 t 6f m/io# valid delay 0.8 5.9 ns 8 t 6g a16Ca3 valid delay 0.5 6.6 ns 8 t 6h a31Ca17 valid delay 0.6 6.6 ns 8 t 7 ads#, adsc#, ap, a31Ca3, pwt, pcd, be7#Cbe0#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 9 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 8 4 t 8b pchk# valid delay 1.0 7.0 ns 8 4 t 9a breq valid delay 1.0 8.0 ns 8 4 t 9b smiact# valid delay 1.0 7.3 ns 8 4 t 9c hlda valid delay 1.0 6.8 ns 8 t 10a hit# valid delay 1.0 6.8 ns 8 t 10b hitm# valid delay 0.7 6.0 ns 8 t 11a pm1Cpm0, bp3Cbp0 valid delay 1.0 10.0 ns 8 t 11b prdy valid delay 1.0 8.0 ns 8 t 12 d63Cd0, dp7Cdp0 write data valid delay 1.3 7.5 ns 8 t 13 d63Cd0, dp3Cdp0 write data float delay 10.0 ns 9 1 t 14 a31Ca5 setup time 6.0 ns 10 26 t 15 a31Ca5 hold time 1.0 ns 10 t 16a inv, ap setup time 5.0 ns 10 t 16b eads# setup time 5.0 ns 10 t 17 eads#, inv, ap hold time 1.0 ns 10 note: see table 21 for notes.
pentium ? processor with mmx? technology datasheet 39 t 18a ken# setup time 5.0 ns 10 t 18b na#, wb/wt# setup time 4.5 ns 10 t 19 ken#, wb/wt#, na# hold time 1.0 ns 10 t 20 brdy#, brdyc# setup time 5.0 ns 10 t 21 brdy#, brdyc# hold time 1.0 ns 10 t 22 ahold, boff# setup time 5.5 ns 10 t 23 ahold, boff# hold time 1.0 ns 10 t 24a buschk#, ewbe#, hold setup time 5.0 ns 10 t 24b pen# setup time 4.8 ns 10 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 10 t 25b hold hold time 1.5 ns 10 t 26 a20m#, intr, stpclk# setup time 5.0 ns 10 notes 12, 16 t 27 a20m#, intr, stpclk# hold time 1.0 ns 10 13 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 10 notes 12, 16, 17 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 10 13 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clk notes 15, 17 t 31 r/s# setup time 5.0 ns 10 notes 12, 16, 17 t 32 r/s# hold time 1.0 ns 10 13 t 33 r/s# pulse width, async. 2.0 clk notes 15, 17 t 34 d0Cd63, dp0C7 read data setup time 2.8 ns 10 t 35 d0Cd63, dp0C7 read data hold time 1.5 ns 10 t 36 reset setup time 5.0 ns 11 notes 12, 16 t 37 reset hold time 1.0 ns 11 13 t 38 reset pulse width, v cc & clk stable 15.0 clk 11 17 t 39 reset active after v cc & clk stable 1.0 ms 11 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 11 notes 12, 16, 17 t 41 reset configuration signals (init, flush#) hold time 1.0 ns 11 13 t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clk to reset falling edge, note 16 t 42b reset configuration signals (init, flush#, brdyc#, buschk#) hold time, async. 2.0 clk to reset falling edge, note 27 table 20. ac specifications (sheet 2 of 4) see table 16 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes note: see table 21 for notes.
pentium ? processor with mmx? technology 40 datasheet t 42c reset configuration signals (brdyc#, buschk#) setup time, async. 3.0 clk to reset falling edge, note 27 t 43a bf0, bf1, cputyp setup time 1.0 ms 11 to reset falling edge, note 22 t 43b bf0, bf1, cputyp hold time 2.0 clk to reset falling edge, note 22 t 43c apicen, be4# setup time 2.0 clk to reset falling edge t 43d apicen, be4# hold time 2.0 clk to reset falling edge t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 7 t 46 tck high time 25.0 ns 7 2 v, note 1 t 47 tck low time 25.0 ns 7 0.8 v note 1 t 48 tck fall time 5.0 ns 7 2.0 v C 0.8 v, notes 1, 8, 9 t 49 tck rise time 5.0 ns 7 0.8 v C 2.0 v, notes 1, 8, 9 t 50 trst# pulse width 40.0 ns 13 asynchronous, note 1 t 51 tdi, tms setup time 5.0 ns 12 7 t 52 tdi, tms hold time 13.0 ns 12 7 t 53 tdo valid delay 2.5 20.0 ns 12 8 t 54 tdo float delay 25.0 ns 12 notes 1, 8 t 55 all non-test outputs valid delay 2.5 20.0 ns 12 notes 3, 8, 10 t 56 all non-test outputs float delay 25.0 ns 12 notes 1, 3, 8, 10 t 57 all non-test inputs setup time 5.0 ns 12 notes 3, 7, 10 t 58 all non-test inputs hold time 13.0 ns 12 notes 3, 7, 10 apic ac specifications t 60a picclk frequency 2.0 16.66 mhz 7 t 60b picclk period 60.0 500.0 ns 7 t 60c picclk high time 15.0 ns 7 t 60d picclk low time 15.0 ns 7 t 60e picclk rise time 0.15 2.5 ns 7 t 60f picclk fall time 0.15 2.5 ns 7 t 60g picd1Cpicd0 setup time 3.0 ns 10 to picclk t 60h picd1Cpicd0 hold time 2.5 ns 10 to picclk t 60i picd1Cpicd0 valid delay (ltoh) 4.0 38.0 ns 8 from picclk, note 28 t 60j picd1Cpicd0 valid delay (htol) 4.0 22.0 ns 8 from picclk, note 28 t 80a pbreq#, pbgnt#, phit# flight time 0.0 2.0 ns 8 notes 11, 24 table 20. ac specifications (sheet 3 of 4) see table 16 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes note: see table 21 for notes.
pentium ? processor with mmx? technology datasheet 41 t 80b phitm# flight time 0.0 1.8 ns 8 notes 11, 24 t 83a a31Ca5 setup time 3.7 ns 10 18 t 83b d/c#, w/r#, cache#, lock#, scyc setup time 4.0 ns 10 notes 18, 21 t 83c ads#, m/io# setup time 5.8 ns 10 notes 18, 21 t 83d hit#, hitm# setup time 6.0 ns 10 notes 18, 21 t 83e hlda setup time 6.0 ns 10 notes 18, 21 t 84a cache#, hit# hold time 1.0 ns 10 notes 18, 21 t 84b ads#, d/c#, w/r#, m/io#, a31Ca5, hlda, scyc hold time 0.8 ns 10 notes 18, 21 t 84c lock# hold time 0.9 ns 10 notes 18, 21 t 84d hitm# hold time 0.7 ns 10 notes 18, 21 t 85 dpen# valid time 10.0 clk notes 18, 19, 23 t 86 dpen# hold time 2.0 clk notes 18, 20, 23 t 87 apic id (be3#Cbe0#) setup time 2.0 clk 11 to falling edge of reset, note 23 t 88 apic id (be3#Cbe0#) hold time 2.0 clk 11 from falling edge of reset, note 23 t 89 d/p# valid delay 1.0 8.0 ns 8 primary processor only table 20. ac specifications (sheet 4 of 4) see table 16 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes note: see table 21 for notes.
pentium ? processor with mmx? technology 42 d atashe e t t a b l e 21. notes for t a b l e 20 no t es: n o t e s 2 , 6 a n d 1 4 a r e g e n e r a l a n d a p p l y t o a ll s t a n d a r d tt l s i g n a l s u se d w i t h t h e p e n t i u m ? p r o c e s so r f a m i l y . e a c h v a l i d d e l a y is s p e c i f i e d for a 0 p f l o a d . t he s y s t em d e s i gn er s h o u ld u s e i/o b u f f er m o d els to a c c o u nt f or s i g n a l f l i g h t t im e d e l a ys. 1 . n o t 1 0 0% t e s t e d . gu a r a n t ee d b y d e s i g n / c h a r a c t e r i za t i o n . 2 . t tl i n p u t t e s t w a v e f o r m s are a ss u m e d t o b e 0 t o 3 v tr a n s i t io n s w i t h 1 v / ns r i se a nd f a l l ti m e s. 3 . n o n- t e s t o u t p u ts a nd i n p u ts a r e t he n o r m al o ut p ut or i n p u t s i g n a ls ( b e s i d es t c k, t r s t # , t d i, t d o a nd t m s ). t h e se t i m i n g s c orr e s p o n d to t h e r e s p o n s e o f t h e s e s i g n als d ue t o b o u n d a r y sc an o p e ra t io n s . 4 . a p ch k # , f e rr # , h l d a , i e rr # , l o c k # a n d p c h k # a r e g l i t c h - f r e e ou t p u t s . gl i t c h - f r e e s i g n a l s m o n o to n i c a l ly t r a n s i ti o n w it h o u t f a l se tr a n s i ti o n s . 5 . 0 . 8 v / ns c l k i n p ut ri s e /f a l l ti m e 8 v / n s . 6 . 0 . 3 v / ns i n p u t r i s e / f a ll t i me 5 v / n s . 7 . r e f e r e n c e d t o t c k r i s i n g e d g e . 8 . r e f e r e n c e d t o t c k f a l l i n g e d g e . 9 . 1 n s c a n b e a d d e d t o the m a x i m u m t c k ri s e a n d fa l l t i m es f or e v ery 1 0 m h z o f f r e q u e n c y b e l o w 3 3 m h z . 1 0 . d u ri n g d e b u g g i n g, do n o t u s e the b o u n d ary sc an t i m i n g s (t 55 to t 58 ). 1 1 . t h i s is a f l i g h t t im e sp e c i f i c a t i o n , t ha t i nc l u d e s b o t h f l i g h t t i m e a n d c l oc k sk e w . t h e f l i g h t t i m e i s t h e t i m e f rom w h ere t h e u n l o a d ed d ri v er cr o s s e s 1.5 v (5 0 % of m i n v cc ) , t o w h e r e t h e r e c e i v e r c r o s s e s t h e 1 . 5 v l e v e l ( 5 0 % o f m i n v cc ). s ee f i g u r e 1 4 . t h e m in i m um f l i g ht ti m e m i n us t h e c l o c k s k e w m u s t b e gr e a t er t h a n z e ro. 1 2 . s e t u p t i me i s r e q u i r e d t o g u a r a n t e e r e c o g n i t i o n o n a s p ec i f i c c l o c k . p e n t i u m ? pr o c e s s o r w i th m m x ? t e c h n o l o g y m u s t m e e t t h i s s p e c i f i c at i on f o r d u a l p r o c e s s o r o p e rat i on f o r t he f l ush# a n d reset s i g n a l s . 1 3 . h o ld t i m e is r e q u i r ed t o g u a r a n t ee r e c o g n i ti o n on a s p e c i f ic c l o c k. p e n t i u m p r o c e ss or w i t h m m x t e c h n o l o gy m u s t m e e t t h is s p e c if i c a ti o n f o r d u al p ro c e ss or o p er a ti o n f o r t h e f l u s h # an d r e set s i g n a l s. 1 4 . a l l tt l t i m i n g s a r e r e f e r e n c e d f r o m 1 . 5 v . 1 5 . t o g u a r a n t e e p r o p e r a s y nc h r o n o u s r e c og n i t i o n , t h e s i g n a l m u s t h a v e be e n d e a ss e r t e d ( i n a c t i v e ) f o r a m i n i mu m o f t w o c l o ck s b e f o r e b e i n g r e t u r n e d ac t i v e a n d m u s t m e e t t h e m i n i m u m p u l s e w i d t h. 1 6 . t h i s i n p u t m a y b e d r i ve n as y n c h r o n o u s l y . h o w e v e r , w h e n o pe r a t i n g t w o p r o ce s s o r s i n d u a l p r oc e s s i n g mo d e , f l u s h # a n d r es e t mu s t b e a s s e r t e d s y nc h r o n o u s l y t o b o t h p r o c e s so r s . 1 7 . w h e n dr i v e n a s y n c hr o n o u s l y , r e s e t , n m i , fl u s h #, r /s # , i n i t a n d s m i # m u st be d e a s s e rted ( i n a c t i v e) f o r a m i n i mu m o f t w o c l o ck s b e f o r e b e i n g r e t u r ne d ac t i v e . 1 8 . t im i n g s a r e v a l i d o n l y w he n d u a l p r o c es s o r i s p r e s e n t. 1 9 . m a x i m u m t i m e dp e n# i s v a l i d from r i s ing e d g e of rese t . 2 0 . m i n i m u m ti m e d pe n # i s v a lid a ft e r f a l l i n g ed ge of r es e t . 2 1 . t h e d / c # , m / io # , w / r # , c a ch e # a n d a 3 1 C a 5 si g n a l s a r e s am p l e d o n l y o n t h e c l k t h a t a d s # i s a c t i v e. 2 2 . i n o rd e r t o o v err i de t h e in t er n al d ef a u l ts a nd g u a r a n tee t h at t h e bf 1 Cb f 0 in p u t s re m a i n s t a b le w h i le r e s e t i s a c t i v e , t h e s e p i n s s h o u l d b e s t r a p p e d d i r e c t l y t o o r t h r o u g h a p u l l - u p / p u l l - d o w n r e s i s t o r t o v cc3 o r g ro u n d . d r i v i n g t h e s e p i n s w i th a c t i v e l o g ic is n ot re c o m m e n d ed u nl e s s s t a b il i ty d u ri n g reset c an b e g u a ra n t e e d . s i m i l ar l y , c p u typ s h o u ld a l s o b e s t ra p p e d d i re c tly t o o r t hr o u g h a p u l l- u p / p u ll - d o w n r e s i s t o r t o v cc3 o r g r o u n d . 2 3 . r e se t i s s y n c h r o n o u s i n d u a l p r o c e s si n g m o d e . a l l s i g n a l s w h ic h h a ve a s e t u p o r h o l d t i m e w i t h r e s p e c t t o a f a l l i n g o r r i s i ng e d g e o f reset in u p m o d e , s h o u ld be m e a s ur e d with r e s p e c t to the f i r s t p ro c e s s or c l o c k e d g e in w h i c h r e set is s a m p led e it h er a c t i ve o r i n a c t i ve i n d u a l pr o c e s s i ng m o d e. 2 4 . t h e p h i t # a n d p h i t m# s ig na l s o p e r a t e a t t h e c o r e f r e q u e n c y . 2 5 . t h e se s i g n a ls a re m e a s u r ed on t h e ri s i n g e d ge of a dj a c e n t c l ks at 1 . 5 v . t o e n s u re a 1:1 r e l a ti o n s h ip b e t w e e n t h e a m p l it u de of the i n p u t j it t er a nd t h e i n t e rn a l a nd e x t e rn a l c l o c k s , t h e j i t ter f re q u e n c y s p e c tr u m s h ou ld n o t h a v e a n y p o w e r s p e c t r um p ea k i n g b e t w e e n 5 0 0 k h z a n d 1 / 3 o f t h e c l k o p e r a t i ng f r e q u e n c y . t h e a mo u n t o f j i t t e r p r e s e n t m u s t b e a cc o u n t e d f o r a s a c o mp o n e n t o f c l k sk e w b e t w e e n d e v i c es . t h e i nt e r n al c l o c k g e n er a tor re q u i res a c o n s ta n t f re q u e n c y c l k i n p u t t o w it h in 2 50 p s. t h er e f o re, t h e c lk i n p u t c a n no t b e ch a n g e d dy n a m i c a l l y . 2 6 . i n d u a l p r o c es s i n g m o d e , t i mi n g t 14 is r e p l a c e d b y t 83a . t i m i ng t 14 i s r e q u i r e d f o r e x t e r n a l s n o o p i n g ( e . g . , a d d re s s s et u p to t h e c l k i n w h i ch e a d s # is s a m p l ed a c t i v e) i n b o t h u n i p ro c e s s or a n d d u a l pr o c e s s o r mo d e s . 2 7 . b r d y c # a n d b u s c h k# a r e u s ed a s r e s et c o n f i g ur a ti o n s i g n a l s to s e l e c t b uff e r s i z e. 2 8 . t h i s as s um e s a n ex t e r n a l p u l l - u p r es i s t o r t o v cc a n d a l u mp e d c a p a c i t i v e l o a d . t h e pu ll - u p r e s i s t o r m u s t b e b e t w e en 3 0 0 w an d 1 k w , t h e c a p a c i t a n c e m u s t b e b e t w e e n 2 0 p f a n d 1 20 p f , a n d t h e r c p r o d uc t mu s t b e b e t w e e n 6 n s an d 3 6 n s . v o l f o r p i cd 1 C p i c d 0 i s 0 . 5 5 v .
pentium ? processor with mmx? technology datasheet 43 figure 7. clock waveform figure 8. valid delay timings figure 9. float delay timings clk p6cb761 a 2.0v 0.8v 1.5v t z t x t y t v t w t r t5, t25, t34 (rise time) t f t6, t26, t35 (fall time) t3, t23, t32 (high time) t h t4, t24, t33 (low time) t l t1, t22, t31 (blck, tck, picclk period) = = = = = t p signal valid 1.5v 1.5v t max. x t min. x t x = t6, t8, t9, t10, t11, t12, t60i, t60j, t80a, t89
pentium ? processor with mmx? technology 44 datasheet figure 10. setup and hold timings figure 11. reset and configuration timings
pentium ? processor with mmx? technology datasheet 45 figure 12. test timings figure 13. test reset timings
pentium ? processor with mmx? technology 46 datasheet figure 14. 50 percent v cc measurement of flight time

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